Version Differences
Direct3D 8 - Vertex Shader - Version Differences
Last edited 2026-01-27
Each version supports a different number of maximum instruction slots.
It's important to use the D3D8 Vertex Shader (vs.1.0 or vs.1.1).
Using (vs_1_0 or vs_1_1) instead will result in the effect not working.
The meaning of colors in the Type, Version and Working column:
|
Color |
Description |
|
Green |
The version works in Fusion. |
|
Yellow |
The version has not been confirmed to work in Fusion. |
|
Red |
The version does not work in Fusion. |
Vertex Shader Version Comparison (Wikipedia)
|
Type |
Version |
Working? |
Number of instruction slots |
Max number of instructions executed |
Instruction predication |
Temp register |
Number constant registers |
Address register |
Static flow control |
Dynamic flow control |
Dynamic flow control depth |
Vertex texture fetch |
Number of texture samplers |
Geometry instancing support |
Bitwise operators |
Native integers |
Note |
|
asm |
vs.1.0 |
No |
128 |
128 |
No |
12 |
>= 96 |
No |
No |
No |
0 |
No |
0 |
No |
No |
No |
Compiler throws a warning about lack of support for vs.1.0 and uses vs.1.1. |
|
asm |
vs.1.1 |
Unknown |
128 |
128 |
No |
12 |
>= 96 |
Yes |
No |
No |
0 |
No |
0 |
No |
No |
No |
|
">= 96" for Number constant registers:
- The specification guarantees at least 96 constant registers.
- The GPU can have more, but not less.
- Number of instruction slots - The maximum number of assembly instructions (instruction slots) that a saved vertex shader program can contain.
- Max number of instructions executed - The maximum number of instructions the GPU can execute for a single vertex when running a vertex shader.
- Instruction predication - A predicate instruction mechanism that allows conditional execution without expensive branching: instructions marked with a predicate write their result only if the predicate is true.
- Temp register - Temporary registers (r0, r1, ...) are used to store intermediate values of shader computations (local variables). The limit on the number of temp registers determines how much intermediate data can be stored without additional cost.
- Number constant registers - Number of constant registers intended for values sent from the application (e.g. matrices, light positions).
- Address register - Address register (e.g. a0) used for indirect addressing/tables.
- Static flow control - Loops/conditions that the compiler can unroll or optimize because their number/nature is known at compilation.
- Dynamic flow control - True conditions and loops depending on data calculated at runtime (if/else, while, for with variable condition) - that is, control flow depending on values calculated during shader execution.
- Dynamic flow control depth - Maximum allowed nesting depth for dynamic control statements (if/loop etc.) - This determines how deep data-dependent conditions/loops can be nested.
- Vertex texture fetch - Ability to sample textures inside the vertex shader.
- Number of texture samplers - The number of available texture samplers/slots that the vertex shader can use for sampling (if the VF is capable of fetching textures).
- Geometry instancing support - Geometry instantiation support: ability to read instance ID and draw multiple copies of the same mesh with different parameters in the vertex shader.
- Bitwise Operators - Support for bitwise logical operations (AND, OR, XOR, bit shifts <<, >>).
- Native Integers - Support for integer types (int), the lack of which means that everything is a floating-point number (float), which makes precision difficult.
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